|
週次 |
日期 |
單元主題 |
|
第1週 |
|
Ch 1 Introduction, Number Systems |
|
第2週 |
|
Ch 2 Boolean Algebra |
|
第3週 |
|
Ch 3 Boolean Algebra (Continued) |
|
第4週 |
|
Ch 4 Applications of Boolean Algebra |
|
第5週 |
|
Ch 5 Karnaugh Maps; Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
|
第6週 |
|
Quiz 1 (Ch 1-4); Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
|
第7週 |
|
Ch 8 Combinational Ckt Design (skip Fig 8-12, 8-14) |
|
第8週 |
|
Ch 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8, and Shannon’s expansion (eqs. 9-10~12) will be included in the exam.) |
|
第9週 |
|
Review Session; Midterm (Ch1-9) |
|
第10週 |
|
Ch 11 Latches and FFs, Combinational Circuit Design using Altera Quartus II |
|
第11週 |
|
Ch 12 Registers and Counters |
|
第12週 |
|
Ch 12 Registers and Counters |
|
第13週 |
|
Ch 13 Analysis of Clocked Sequential Ckts, Sequential Circuit Design using Altera Quartus II |
|
第14週 |
|
Ch 14 Derivation of State Graphs and Tables ( Skip Examples 2 & 3 in Sec. 14.3) |
|
第15週 |
|
Quiz 2 (Ch 11-13) |
|
第16週 |
|
Ch 15 Reduction of State Tables (15.1 to 15.3) |
|
第17週 |
|
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
|
第18週 |
|
Final Exam |